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--- ad7190 [2016/02/23 11:41]
karl [Holding Time of last Data Bit]
+++ ad7190 [2017/04/04 06:45] (aktuell)
karl [Holding Time of last Data Bit]
@@ Zeile 37: / Zeile 37: @@
 Image based on [[https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#/media/File:SPI_timing_diagram2.svg|this from Wikipedia]], created by Cburnett.
-As a workaround perhaps a 2nd order RC-lowpass filter could help to implement a small phase shift. \\
-Another possibility would be a software implementation of the SPI on the master side, which would sample the MISO line just before rising the clock line.
+=== Workarounds ===
+  * As a workaround perhaps a 2nd order RC-lowpass filter could help to implement a small phase shift. With 2x 1kΩ and 2x 100pF we get a delay of about 100ns (0.2 x VCC threshold), and the signal integrity is guaranteed until 500kHz of clock frequency. {{:ad7190:2016-02-24_003.png?direct&600|From the ATmega328 datasheet}} {{:ad7190:2016-02-24_004.png?direct&600|LTspice simulation}}\\
+  * Another possibility would be a software implementation of the SPI on the master side, which would sample the MISO line just before rising the clock line.
+{{tag>english adc product noise technical}}

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