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ad7190 [2016/02/24 16:12] karl |
ad7190 [2017/04/04 06:45] (aktuell) karl [Holding Time of last Data Bit] |
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* As a workaround perhaps a 2nd order RC-lowpass filter could help to implement a small phase shift. With 2x 1kΩ and 2x 100pF we get a delay of about 100ns (0.2 x VCC threshold), and the signal integrity is guaranteed until 500kHz of clock frequency. {{: | * As a workaround perhaps a 2nd order RC-lowpass filter could help to implement a small phase shift. With 2x 1kΩ and 2x 100pF we get a delay of about 100ns (0.2 x VCC threshold), and the signal integrity is guaranteed until 500kHz of clock frequency. {{: | ||
* Another possibility would be a software implementation of the SPI on the master side, which would sample the MISO line just before rising the clock line. | * Another possibility would be a software implementation of the SPI on the master side, which would sample the MISO line just before rising the clock line. | ||
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